1. Field of Invention
This invention relates to an output control circuit for use with a transfer device in which a number of unit circuits that shift a starting pulse sequentially in synchronization with a clock signal are in cascade connection with each other, a driving circuit, an electro-optic apparatus, and an electronic instrument.
2. Description of Related Art
A driving circuit for an electro-optic apparatus, for example, a liquid crystal apparatus, can be formed by a data line driving circuit and scan line driving circuit that supply a data line signal and scan signal in, a predetermined timing, to data lines and scan lines wired in an image display area. A sampling circuit can be provided in a later stage of the data line driving circuit. The sampling circuit samples an image signal and supplies the image signal to each of the data lines based on each of sampling signals supplied from the data line driving circuit.
The conventional data line driving circuit generally has a shift resistor that shifts the starting pulse and an output control circuit that generates the sampling signals based on an output signal of each stages in the shift resistor.
Although it is ideal that each of the sampling signals becomes sequentially active exclusively, an enabling period of a sampling signal may overlap with an enabling period of a subsequent sampling signal by delay in a logic circuit forming the data line driving circuit.
To solve such problem, it can be considered that an enabling signal for enabling the sampling signals output from the output control circuit or an inhibiting signal for inhibiting the sampling signals is supplied, thereby pulse width of the sampling signals are controlled. However, when the data line driving circuit has a high operating frequency, since the period for inhibiting an adjacent sampling signal is shortened, the enabling signal and the inhibiting signal include an extremely high frequency component. On the other hand, since wiring for supplying the enabling signal and inhibiting signal has a floating capacitance, there is a certain limit in transmitting a high frequency signal through such wiring. Therefore, there has been a problem that when the data line driving circuit has a high operating frequency, the enabling signal and inhibiting signal cannot be transmitted adequately, resulting in overlap among the adjacent sampling signals.
Even when the enabling signal and inhibiting signal can be transmitted and the pulse width of the sampling signal can be limited, the reduced pulse width of the sampling signal causes a following problem. That is, while the image signal is supplied to the data line during an active period of the sampling signal, since the data line has a capacitance in itself, when the active period of the sampling signal is shortened, the image signal cannot be written in the data line adequately. This point becomes a more significant problem as the operating frequency of the data line driving circuit is increased.